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N-bits successive approximation register analog-to-digital converting circuit
Yan ZHU; Chi-Hang CHAN; U-Fat CHIO; Sai-Weng SIN; Seng-Pan U; Rui Paulo Da Silva MARTINS; Franco MALOBERTI
2013
Rights HolderUniversity of Macau
CountryUnited States
Subtype发明专利
Abstract

The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACarray and a sampling capacitor CSp, an n-type capacitor network including a DACnarray and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch

Application Date2011-06-01
Patent NumberUS20120306679A1
Language英语
Status已授权
全文获取链接
Document TypePatent
专题INSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
AffiliationUniversity of Macau, Macau
First Author AffilicationUniversity of Macau
推荐引用方式
GB/T 7714
Yan ZHU,Chi-Hang CHAN,U-Fat CHIO,et al. N-bits successive approximation register analog-to-digital converting circuit. US20120306679A1[P]. 2013-01-01.
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