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A 3.65 mW 5 bit 2GS/s flash ADC with built-in reference voltage in 65nm CMOS process
Yang J.; Chen Y.; Qian H.; Wang Y.; Yue R.
2012-12-01
Source PublicationICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
AbstractA low power 5 bit 2 GS/s flash ADC is designed for 60GHz wireless communication system using 65 nm CMOS process. The proposed ADC is implemented by calibrated comparators array with built-in reference voltage instead of resistor reference ladder, which will reduce the power consumption. Simulation results show that, the ADC obtains ENOB of 4.99 bit at low input frequency and 4.72 bit at Nyquist bandwidth, consuming 3.65mW with a 1.2 V supply voltage, achieving a low FoM value of 57 fJ/conversion step. © 2012 IEEE.
DOI10.1109/ICSICT.2012.6467783
URLView the original
Language英語
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Document TypeConference paper
CollectionUniversity of Macau
AffiliationTsinghua University
Recommended Citation
GB/T 7714
Yang J.,Chen Y.,Qian H.,et al. A 3.65 mW 5 bit 2GS/s flash ADC with built-in reference voltage in 65nm CMOS process[C],2012.
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