UM
A 1.5GS/s 6bit 2bit/Step asynchronous time interleaved SAR ADC in 65nm CMOS
Wang Z.; Chen Y.; Qian H.
2012-12-01
Source PublicationECS Transactions
Volume44
Issue1
Pages121-125
AbstractThe Gbps data rate wireless communication applications such as 60GHz wireless transceiver systems necessitate low-power highspeed Analog to Digital Converters (ADCs) to convert RF/IF signals into digital form for subsequent baseband processing. By contrast with flash ADCs that suffer from high power consumption and large area, Successive Approximation Register (SAR) ADCs have low power dissipation and occupy a small area. This paper presents a 6bit, 1.5GS/s asynchronous time interleaved SAR ADC which was designed in a 65nm standard CMOS process. The sample rate of 1.5GS/s was achieved by four single ADCs time-interleaved. Single sample and hold is applied in this work to avoid the effect of offset and timing-skews. Simulation results show that the proposed SAR ADC gives SNDR of 35.5dB, SFDR of 41.9dB and ENOB of 5.61 at nyquist rate. © The Electrochemical Society.
DOI10.1149/1.3694305
URLView the original
Language英語
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionUniversity of Macau
AffiliationTsinghua University
Recommended Citation
GB/T 7714
Wang Z.,Chen Y.,Qian H.. A 1.5GS/s 6bit 2bit/Step asynchronous time interleaved SAR ADC in 65nm CMOS[C],2012:121-125.
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