UM
An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS
Wang X.S.2; Chan C.-H.4; Du J.2; Wong C.-H.2; Li Y.2; Du Y.2; Kuan Y.-C.3; Hu B.2; Chang M.-C.F.2
2018-08-07
Source PublicationDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2018-June
Pages88-91
AbstractThis paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2×8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
DOI10.1109/RFIC.2018.8429007
URLView the original
Language英語
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Document TypeConference paper
CollectionUniversity of Macau
Affiliation1.NovuMind Inc.
2.University of California, Los Angeles
3.National Chiao Tung University Taiwan
4.Universidade de Macau
Recommended Citation
GB/T 7714
Wang X.S.,Chan C.-H.,Du J.,et al. An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS[C],2018:88-91.
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