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A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS
Yin J.; Luong H.C.
2014
Source PublicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
AbstractEmploying a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of-94dBc/Hz in band and of-136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm. © 2014 IEEE.
DOI10.1109/VLSIC.2014.6858394
URLView the original
Language英語
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Document TypeConference paper
专题University of Macau
AffiliationHong Kong University of Science and Technology
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GB/T 7714
Yin J.,Luong H.C.. A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS[C],2014.
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