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A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration
Qiu L.1; Kai T.1; Zhu Y.2; Siek L.1; Zheng Y.1; Seng-Pan U.2
2017-02-06
Conference NameIEEE Asian Solid-State Circuits Conference (A-SSCC)
Source Publication2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
Pages77-80
Conference DateNOV 07-09, 2016
Conference PlaceToyama, JAPAN
Abstract

This paper presents a 10-bit 1GS/s 4-way time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To reduce the time skew among the TI channels, the master clock based sampling technique is adopted that can effectively suppress the interleaving spurs to -54dB at Nyquist input. Morever, a tap-interpolating fractional delay (TIFD) filters based time skew calibration technique is proposed, which operates at background and can further reduce the interleaving spurs to be less than -70dB. The prototype was fabricated in a 65nm CMOS technology. The measurement results show that the ADC operating at 1GS/s achieves a SNDR of 49.6dB and SFDR of 61.6dB at Nyquist input resulting in a figure of merit (FoM) of 32fJ/conversion-step.

KeywordSar Adcs Time Skew Calibration Time-interleaved
DOI10.1109/ASSCC.2016.7844139
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000401471500020
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Citation statistics
Cited Times [WOS]:8   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Affiliation1.Nanyang Technological University
2.Universidade de Macau
Recommended Citation
GB/T 7714
Qiu L.,Kai T.,Zhu Y.,et al. A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration[C],2017:77-80.
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