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A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs
Chio U.-F.2; Wei H.-G.2; Zhu Y.2; Sin S.-W.2; Seng-Pan U.2; RPMartins2
2008-12-01
Conference NameIEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008)
Source PublicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages1164-1167
Conference DateNOV 30-DEC 03, 2008
Conference PlaceMacao, PEOPLES R CHINA
Abstract

Novel self-timing switch-driving registers for high-speed Successive Approximation Register (SAR) ADC is proposed. This circuit can provide fast charging path from comparator output to DAC array of SAR ADC and store the comparison results simultaneously at each approximation bit-cycle. The propagation delay from input to output of the register is about 60ps only in a 90nm CMOS process. By using this technique, the 5-bit SAR ADC achieves 30.3dB SNDR with 285MS/s high sampling-rate, power consumption is 10.5mW. © 2008 IEEE.

DOIhttp://doi.org/10.1109/APCCAS.2008.4746232
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Computer Science, Information Systems ; Engineering, Electrical & Electronic
WOS IDWOS:000268007100287
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Citation statistics
Cited Times [WOS]:5   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
Recommended Citation
GB/T 7714
Chio U.-F.,Wei H.-G.,Zhu Y.,et al. A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs[C],2008:1164-1167.
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