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A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing
Liang Qi1,2; Sai-Weng Sin1,2; Seng-Pan, U.1,2; Franco Maloberti1; Rui Paulo Martins1,2
2017-10
Source PublicationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN1549-8328
Volume64Issue:10Pages:2641-2654
Abstract

This paper presents a discrete time 2-1 MASH Delta-Sigma (Delta Sigma) modulator with multirate opamp sharing for analog-to-digital converters, targeting the optimization of power efficiency in active blocks, such as opamps and quantizers. Through the allocation of different settling times to the opamps and by adopting the multirate technique, the power of the shared opamps is utilized more efficiently, and the 4-b successive approximation register quantizer and the data weighted averaging block in the first stage enjoy additional operation time. Moreover, a detailed analysis and related simulations are presented to validate the enhanced opamp power efficiency in the proposed sharing scheme. The 65-nm CMOS experimental chip running at multirate 120/240 MHz achieves a mean signal-tonoise and distortion ratio (SNDR) of 77.1 dB for a 5-MHz bandwidth, consuming 4.2 mW from a 1.2 V supply and occupying 0.066-mm(2) core area. It exhibits a Walden figure of merit (FoM) of 69.7 fJ/conv-step and a Schreier FoM of 167.9 dB based on SNDR.

KeywordAnalog-to-digital Converter (Adc) Discrete-time (Dt) Delta Sigma (Delta Sigma) Modulator Multi-stage Noise Shaping (Mash) Wideband Power-efficient Opamp Sharing Multirate Successive Approximation Register (Sar) Quantizer
DOI10.1109/TCSI.2017.2693921
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000413831600001
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
Fulltext Access
Citation statistics
Cited Times [WOS]:7   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Macau 999078, Peoples R China
2.Univ Macau, FST ECE, Macau 999078, Peoples R China
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Liang Qi,Sai-Weng Sin,Seng-Pan, U.,et al. A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2017,64(10):2641-2654.
APA Liang Qi,Sai-Weng Sin,Seng-Pan, U.,Franco Maloberti,&Rui Paulo Martins.(2017).A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,64(10),2641-2654.
MLA Liang Qi,et al."A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 64.10(2017):2641-2654.
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