Please use this identifier to cite or link to this item: http://repository.umac.mo/handle/10692/1387
Title: A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration
Authors: Chio, U Fat
Chan, Chi Hang (陳知行)
Choi, Hou Lon
Sin, Sai Weng (冼世榮)
U, Seng Pan (余成斌)
Martins, Rui Paulo Da Silva (馬許願)
Issue Date: Sep-2011
Publisher: IEEE
Citation: 2011 Proceedings of the ESSCIRC (ESSCIRC), Sep. 2011, p. 363-366
Abstract: This paper reports a 7-bit 300-MS/s subranging ADCfabricated in standard 65nm CMOS, which utilizes embeddedreference and gain loss error calibration techniques. A sharedpassive capacitive DAC array performs the input sampling inquantization mode and reference generation in calibration mode,providing a linear, accurate and compact calibrationimplementation. As a consequence of the developed calibrationtechniques, uniform-sized dynamic comparators are employedto reduce the process-mismatch variation and nonlinearity error,when compared with the conventional structures. The ADCachieves peak SNDR of 40.5dB at 300MS/s and 39dB at 400MS/s,with ERBW of 300MHz and 350MHz, respectively. The powerconsumption is 2.3mW only from 1.2-V supply at 300MS/s.
URI: http://hdl.handle.net/10692/1387
ISBN: 978-1-4577-0704-9
Keywords: Analog-to-Digital converters
ADCs
Subranging
Flash
Access: http://www.fst.umac.mo/en/staff/documents/fstsws/24.pdf

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