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Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC
Chen Y.2; Mak P.-I.1; Yang J.2; Yue R.2; Wang Y.2
2015-08-14
Conference Name2015 International Symposium on Signals, Circuits and Systems (ISSCS)
Source PublicationISSCS 2015 - International Symposium on Signals, Circuits and Systems
Conference DateJUL 09-10, 2015
Conference PlaceIasi, ROMANIA
Abstract

Two circuit techniques for performance enhancement of high-speed flash ADCs are proposed. A calibration-intensive dynamic comparator features an improved built-in reference voltage generation scheme to alleviate the issue of kickback noise, and a proper reset function to clean the memory effect due to the dielectric relaxation in the capacitors, yielding better static and dynamic linearity performances. The second is a split-ROM encoder, which halves the signaling path to lower the parasitics, while boosting the back-end processing speed with small power. The feasibility of them is demonstrated via a 5-bit flash ADC designed in 65nm CMOS. With 3.69mW of power, the ADC operated at 2GS/s exhibits an ENOB of >4.5 bits up to an ERBW of 3.6GHz. The DNL and INL are within +0.091/-0.071 and +0.066/-0.062 LSB, respectively.

DOIhttp://doi.org/10.1109/ISSCS.2015.7203923
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Theory & Methods ; Engineering, Electrical & Electronic
WOS IDWOS:000380451600003
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Universidade de Macau
2.Tsinghua University
Recommended Citation
GB/T 7714
Chen Y.,Mak P.-I.,Yang J.,et al. Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC[C],2015.
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