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Title: An 11b 60MS/S 2.1mW two-step time-interleaved SAR-ADC with reused S&H
Authors: Sin, Sai Weng (冼世榮)
Ding, Li
Zhu, Yan (朱燕)
Wei, He Gong
Chan, Chi Hang (陳知行)
Chio, U Fat
U, Seng Pan (余成斌)
Martins, Rui Paulo Da Silva (馬許願)
Maloberti, Franco
Issue Date: Sep-2010
Publisher: IEEE
Citation: IEEE European solid-State circuits conference – ESSCIRC 2010, Sep. 2010, p. 218-221
Abstract: An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and subthreshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step.
Keywords: CMOS analogue integrated circuits
Analogue-digital conversion
Operational amplifiers
Access: View full-text via DOI

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