A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure | |
Song Y.3; Zhu Y.3![]() ![]() | |
2018-10-22 | |
Conference Name | 2018 IEEE Symposium on VLSI Circuits |
Source Publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
Volume | 2018-June |
Pages | 203-204 |
Conference Date | 18-22 June 2018 |
Conference Place | Honolulu, HI, USA |
Abstract | This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1-stage and a 5b SAR ADC in the 2-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM. |
DOI | 10.1109/VLSIC.2018.8502382 |
URL | View the original |
Fulltext Access | |
Citation statistics | |
Document Type | Conference paper |
Collection | INSTITUTE OF MICROELECTRONICS |
Affiliation | 1.Xi'an Jiaotong University 2.Instituto Superior Técnico 3.Universidade de Macau |
Recommended Citation GB/T 7714 | Song Y.,Zhu Y.,Chan C.-H.,et al. A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure[C],2018:203-204. |
Files in This Item: | There are no files associated with this item. |
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment