UM
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS
Wang B.4; Sin S.-W.4; Seng-Pan U.4; Malobertr F.4; Martins R.P.4
2018-10-22
Source PublicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2018-June
Pages207-208
AbstractThis paper presents an incremental A/D converter with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise coupling path is then enabled in the exponential phase thus boosting the SQNR exponentially with a few number of clock cycles. The uniform-exponential weight function allows data weighted averaging (DWA) to work well suppressing the DAC mismatch error. Fabricated in 65nm CMOS under 1.2V supply, the ADC achieves an SNDR/DR of 100.8dB/101.8dB with 20kHzBW, 550μW 0.134mm, resulting in FoMw and FoMs of 153fJ/176.4dB (SNDR), respectively.
DOI10.1109/VLSIC.2018.8502384
URLView the original
Language英語
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Document TypeConference paper
CollectionUniversity of Macau
Affiliation1.Synopsys Macau Ltd.
2.Instituto Superior Técnico
3.Università degli Studi di Pavia
4.Universidade de Macau
Recommended Citation
GB/T 7714
Wang B.,Sin S.-W.,Seng-Pan U.,et al. A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS[C],2018:207-208.
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