| A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS | |
| Zhu Y.1; Chan C.-H.1; Zheng Z.-H.1; Li C.1; Zhong J.-Y.1; Martins R.P.1 | |
| 2018-11-01 | |
| Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers
 |
| ISSN | 15498328 |
| Volume | 65Issue:11Pages:3606-3616 |
| Abstract | This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: Noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step. |
| Keyword | passive sharing pipelined-SAR ADC sampling front-end design switch bootstrap technique Time-interleaved ADC |
| DOI | 10.1109/TCSI.2018.2859027 |
| URL | View the original |
| Language | 英語 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Journal article |
| Collection | University of Macau |
| Affiliation | 1.Universidade de Macau 2.Instituto Superior Técnico |
| Recommended Citation GB/T 7714 | Zhu Y.,Chan C.-H.,Zheng Z.-H.,et al. A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2018,65(11):3606-3616. |
| APA | Zhu Y.,Chan C.-H.,Zheng Z.-H.,Li C.,Zhong J.-Y.,&Martins R.P..(2018).A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS.IEEE Transactions on Circuits and Systems I: Regular Papers,65(11),3606-3616. |
| MLA | Zhu Y.,et al."A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS".IEEE Transactions on Circuits and Systems I: Regular Papers 65.11(2018):3606-3616. |
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