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A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs
Yang S.1; Yin J.1; Mak P.-I.1; Martins R.P.1
2019
Source PublicationIEEE Journal of Solid-State Circuits
ISSN00189200
Volume54Issue:1Pages:88-98
Abstract

This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process-voltage-temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digital-controlled delay line (DCDL)-based low-power time-interval comparator and an adjacent-edge selector, to precisely detect the static phase offset (SPO) caused by the VCO frequency drifting in the presence of reference injection. The block-sharing-based SPO detection aids nullifying the circuit-mismatch- and offset-induced deterministic error. Also, for the adjacent edge selector, block sharing between its control generation circuits and the coarse FTL further reduces the power consumption. The varactor-tuned dual multiplexed-ring VCOs (MRVCOs) serve to reduce jitter variation while extending the frequency tuning range. Fabricated in a 28-nm CMOS with a core area of 0.0056 mm, the proposed MDLL covers a tuning range from 1.55 to 3.35 GHz, and exhibits a root-mean-square (rms) jitter of 292 fs at 3-GHz output, under a 200-MHz reference clock. The power consumption is 1.45 mW at a 0.8-V supply, resulting in an FoM of -249 dB favorably comparable with the state of the art.

KeywordClock Multiplier Digital-controlled Delay Line (Dcdl) Frequency-tracking Loop (Ftl) Injection-locked Phase-locked Loop (Il-pll) Multiplying Delay-locked Loop (Mdll) Phase Noise Ring Voltage-controlled Oscillator (Rvco) Root-mean-square (Rms) Jitter
DOIhttp://doi.org/10.1109/JSSC.2018.2870551
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000457637300009
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Citation statistics
Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorYin J.; Mak P.-I.
Affiliation1.Universidade de Macau
2.Instituto Superior Técnico
Recommended Citation
GB/T 7714
Yang S.,Yin J.,Mak P.-I.,et al. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits,2019,54(1):88-98.
APA Yang S.,Yin J.,Mak P.-I.,&Martins R.P..(2019).A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs.IEEE Journal of Solid-State Circuits,54(1),88-98.
MLA Yang S.,et al."A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs".IEEE Journal of Solid-State Circuits 54.1(2019):88-98.
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