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Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC
Li C.1; Chan C.-H.1; Zhu Y.1; Martins R.P.1
2019
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN15498328
Volume66Issue:1Pages:82-93
AbstractThe high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results.
Keywordanalog-to-digital converter (ADC) reference buffer Reference error reference ripple successive-approximation-register (SAR)
DOI10.1109/TCSI.2018.2861835
URLView the original
Language英語
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.Universidade de Macau
2.Instituto Superior Técnico
Recommended Citation
GB/T 7714
Li C.,Chan C.-H.,Zhu Y.,et al. Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2019,66(1):82-93.
APA Li C.,Chan C.-H.,Zhu Y.,&Martins R.P..(2019).Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC.IEEE Transactions on Circuits and Systems I: Regular Papers,66(1),82-93.
MLA Li C.,et al."Analysis of Reference Error in High-Speed SAR ADCs with Capacitive DAC".IEEE Transactions on Circuits and Systems I: Regular Papers 66.1(2019):82-93.
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