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Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity
U Seng-Pan; Martins R.P.; Franca J.E.
1999
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
ISSN02714310
Volume2
Abstract

Novel Switched-Capacitor (SC) delay circuit architectures, all insensitive to capacitance ratio mismatch, non-ideal amplifier's DC offset and 1/f noise with also either narrow or wideband compensation of finite gain error, will be proposed in this paper. A rigorous comparison of the different structures with respect to magnitude, phase and offset errors will be presented for illustrating their effectiveness. Finally, a flexible implementation of arbitrarily longer delay by the proposed circuits will be further developed in some design examples of unit and double unit delay circuits with only one amplifier and unchanged accuracy performance.

DOIhttp://doi.org/10.1109/ISCAS.1999.780618
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000081715200015
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Citation statistics
Document TypeJournal article
CollectionFaculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorU Seng-Pan; Martins R.P.; Franca J.E.
AffiliationUniversidade de Macau
Recommended Citation
GB/T 7714
U Seng-Pan,Martins R.P.,Franca J.E.. Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity[J]. Proceedings - IEEE International Symposium on Circuits and Systems,1999,2.
APA U Seng-Pan,Martins R.P.,&Franca J.E..(1999).Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity.Proceedings - IEEE International Symposium on Circuits and Systems,2.
MLA U Seng-Pan,et al."Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity".Proceedings - IEEE International Symposium on Circuits and Systems 2(1999).
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