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AN I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver
Mak P.-I.1; Ma K.-K.1; Mok W.-I.1; Sou C.-S.1; Ho K.-M.1; Ng C.-M.1; U S.-P.1,2; Martins R.P.1,3
2004-09-07
Conference NameIEEE International Symposium on Circuits and Systems
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1068-1071
Conference DateMAY 23-26, 2004
Conference PlaceVancouver, CANADA
Abstract

A novel pipelined ADC architecture that exhibits both power and area efficiencies is proposed to be accountable for the major baseband functions of the recently introduced two-step-channel-select (2-SCS) low-IF receiver. Such architecture comprises: 1) a sample-and-hold (S/H) front-end implementing Analog-Double Quadrature Sampling (A-DQS) for IF-to-baseband downconversion and IF channel selection, and 2) one OTA-shared pipelined ADC is employed for digitalization both I and Q channels through I/Q-multiplexing. An IC prototype was designed in a 0.35-μm CMOS process with 20-MS/s 8-bit resolution, which has been targeted for 2.4-GHz ISM band standards. The key simulated performances achieved 7.7-b ENOB with INL and DNL within ±0.5 LSB and ±0.34 LSB, respectively. A competitive chip area of only 1.34 mm is achieved, while dissipating an average of 54.5 mW from 2.5 V.

DOIhttp://doi.org/10.1109/ISCAS.2004.1328383
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000223122300268
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Citation statistics
Cited Times [WOS]:2   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Affiliation1.Analog and Mixed-Signal VLSI Laboratory, FST, University of Macau, Macao SAR, China
2.Chipidea Microelectronics (Macao) Ltd.
3.On leave from Instituto Superior Técnico (IST), Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Mak P.-I.,Ma K.-K.,Mok W.-I.,et al. AN I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver[C],2004:1068-1071.
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