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A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications
Ma J.-X.2; Sin S.-W.2; U S.-P.; Martins R.P.1
2006-12-01
Conference NameIEEE International Symposium on Circuits and Systems
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
Pages4305-4308
Conference DateMAY 21-24, 2006
Conference PlaceKos, GREECE
Abstract

A 1.056 GS/s, 5-bit/6-bit switchable flash analog-to-digital converter (ADC) is designed in 0.18-μm CMOS, which is suitable to be used in an OFDM-UWB transceiver. A resolution switchable structure is proposed to optimize power consumption according to the dynamic requirement of the application. Two-stage interpolation and averaging techniques are employed to average the offset of the preamplifiers. Monte Carlo simulation results show that the proposed ADC achieves 4.2b/5.0b ENOB in 5-bit/6-bit working modes with a 413-MHz input signal. The mean value of DNL and INL is 0.32 and 0.56 LSB for 5-bit mode, while 0.47 and 0.62 LSB for 6-bit mode. The analog part consumes 36 mW and 98 mW from a 1.8-V supply in 5-bit and 6-bit operation mode, respectively. © 2006 IEEE.

DOIhttp://doi.org/10.1109/ISCAS.2006.1693581
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000245413504159
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被引频次[WOS]:10   [WOS记录]     [WOS相关记录]
Document TypeConference paper
专题DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
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Ma J.-X.,Sin S.-W.,U S.-P.,et al. A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications[C],2006:4305-4308.
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