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A highly-linear successive-approximation front-end digitizer with built-in sample-and-hold function for pipeline/two-step ADC
Mok W.-I.3; Mak P.-I.3; U S.-P.3; Martins R.P.3
2007-09-27
Conference NameIEEE International Symposium on Circuits and Systems
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1947-1950
Conference DateMAY 27-30, 2007
Conference PlaceNew Orleans, LA
Abstract

This paper presents an improved front-end digitizer for pipeline/two-step ADC. It achieves a high linearity by replacing the front-end stage's sub-ADC from the flash type that involves synchronous operation of several comparators, to the one that uses successive approximation (SA). This shift not only frees the ADC from an extra front-end sample-and-hold circuit, but also guarantees an inherent monotonicity because of no comparator mismatch (since the SA-ADC involves just one comparator in recursive operation). Two examples of a 100-MHz 3.5-bit/stage pipeline ADC and an 11-bit 30-MHz two-step ADC, validate the feasibility of such a digitizer. © 2007 IEEE.

DOIhttp://doi.org/10.1109/ISCAS.2007.378357
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering ; Mathematical & Computational Biology ; Science & Technology - Other Topics ; Imaging Science & Photographic Technology ; Telecommunications
WOS SubjectComputer Science, Artificial Intelligence ; Computer Science, Software Engineering ; Engineering, Biomedical ; Engineering, Electrical & Electronic ; Mathematical & Computational Biology ; Nanoscience & Nanotechnology ; Imaging Science & Photographic Technology ; Telecommunications
WOS IDWOS:000251608402121
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被引频次[WOS]:1   [WOS记录]     [WOS相关记录]
Document TypeConference paper
专题DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Affiliation1.Chipidea Microelectronics (Macao) Ltd
2.Instituto Superior Técnico
3.Universidade de Macau
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Mok W.-I.,Mak P.-I.,U S.-P.,et al. A highly-linear successive-approximation front-end digitizer with built-in sample-and-hold function for pipeline/two-step ADC[C],2007:1947-1950.
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