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A power scalable 6-bit 1.2GS/s flash ADC with power on/off track-and-hold and preamplifier
Wei H.-G.3; Chio U.-F.3; Zhu Y.3; Sin S.-W.3; Seng-Pan U.3; Martins R.P.3
2008-09-19
Conference NameIEEE International Symposium on Circuits and Systems
Source PublicationProceedings - IEEE International Symposium on Circuits and Systems
Pages5-8
Conference DateMAY 18-21, 2008
Conference PlaceSeattle, WA
Abstract

A power scalable 6-bit 1.2GS/s flash Analog-to-Digital Converter (ADC) is designed in 90nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is -0.9/+0.7 LSB and the INL is -0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pJ/conversion-step at Nyquist from 1.2V power supply. ©2008 IEEE.

DOIhttp://doi.org/10.1109/ISCAS.2008.4541340
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering ; Physics ; Telecommunications
WOS SubjectComputer Science, Hardware & Architecture ; Computer Science, Information Systems ; Engineering, Electrical & Electronic ; Physics, Applied ; Telecommunications
WOS IDWOS:000258532100003
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被引频次[WOS]:14   [WOS记录]     [WOS相关记录]
Document TypeConference paper
专题INSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Chipidea Microelectronics (Macao) Ltd
2.Instituto Superior Técnico
3.Universidade de Macau
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Wei H.-G.,Chio U.-F.,Zhu Y.,et al. A power scalable 6-bit 1.2GS/s flash ADC with power on/off track-and-hold and preamplifier[C],2008:5-8.
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