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A Process- and temperature- insensitive current-controlled delay generator for sampled-data systems
Wei H.-G.3; Chio U.-F.3; Zhu Y.3; Sin S.-W.3; Seng-Pan U.3; Martins R.P.3
2008-12-01
Conference NameIEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008)
Source PublicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages1192-1195
Conference DateNOV 30-DEC 03, 2008
Conference PlaceMacao, PEOPLES R CHINA
Abstract

This paper proposes a process- and temperature-insensitive current-controlled delay generator which can be widely used in sampled-data systems. The delay generator provides a large tunable range by adjusting the control current and load capacitance. Full transistor-level simulations, including process corner and Monte-Carlo analysis, are presented. The delay generator is designed in 90nm CMOS technology and consumes 330 μW power from a 1.2V power supply, at a typical case of using 10μA control current and 30fF load capacitance. The process corner simulation results exhibit a typical delay of 2.09 ns with a corner variation of -7.1% / +7.6%. The 500-times process Monte-Carlo simulation obtains a mean of 2.09 ps with a standard-deviation (σ) of 28.9 ps (1.38%). © 2008 IEEE.

DOIhttp://doi.org/10.1109/APCCAS.2008.4746239
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Computer Science, Information Systems ; Engineering, Electrical & Electronic
WOS IDWOS:000268007100294
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.MIPSABG Chipidea, Lda., Portugal
2.Instituto Superior Técnico
3.Universidade de Macau
Recommended Citation
GB/T 7714
Wei H.-G.,Chio U.-F.,Zhu Y.,et al. A Process- and temperature- insensitive current-controlled delay generator for sampled-data systems[C],2008:1192-1195.
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