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Comparator-based successive folding ADC
Chio U.-F.; Choi H.-L.; Chan C.-H.; Wong S.-S.; Sin S.-W.; U S.-P.; Martins R.P.
2009-12-01
Conference NameAsia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Source Publication1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
Pages117-120
Conference DateNOV 19-21, 2009
Conference PlaceShanghai, PEOPLES R CHINA
Abstract

A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue precharging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7 dB at Nyquist input frequency and consumes 430 μW from a 1 V supply in 65 nm CMOS, yielding a FOM of 34 fJ per conversion step. ©2009 IEEE.

DOIhttp://doi.org/10.1109/PRIMEASIA.2009.5397434
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering ; Science & Technology - Other Topics
WOS SubjectEngineering, Electrical & Electronic ; Nanoscience & Nanotechnology
WOS IDWOS:000290197700030
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Citation statistics
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
AffiliationUniversidade de Macau
Recommended Citation
GB/T 7714
Chio U.-F.,Choi H.-L.,Chan C.-H.,et al. Comparator-based successive folding ADC[C],2009:117-120.
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