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Design and experimental verification of a power effective Flash-SAR subranging ADC
U-Fat Chio1; He-Gong Wei1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1; R. P. Martins1,2; Franco Maloberti3
2010-08-01
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume57Issue:8Pages:607-611
Abstract

This brief presents the architectural concept of an optimal subranging ADC, obtained with the cascade of a Flash and a SAR, which is also explored through its practical design and experimental confirmation. The solution doubles the optimal speed of operation of the SAR ADCs at the relative low power cost of a low-resolution Flash. The digital correction method and a capacitor-based DAC ensure nondemanding requirements for the Flash. The effectiveness of the architecture is verified in a 90-nm CMOS chip whose active core area is 0.64 mm. The ADC obtains a peak SNDR of 51.8 dB and SFDR of 63.4 dB at 90 MS/s consuming 13.5mWfrom a 0.9-V supply. Measured DNL and INL are 0.87 LSB and 1.55 LSB, respectively. © 2010 IEEE.

KeywordAnalog-to-digital Converter (Adc) Digital Error Correction (Dec) Flash Adc Sar Adc Subranging Adc
DOIhttp://doi.org/10.1109/TCSII.2010.2050937
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000283130200007
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Cited Times [WOS]:21   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorU-Fat Chio; R. P. Martins; Franco Maloberti
Affiliation1.Analog and Mixed-Signal VLSI Laboratory, Faculty of Science and Technology, University of Macau, Macao, China
2.Instituto Superior Técnico, TU of Lisbon, 1049-001 Lisboa, Portugal
3.Department of Electronics, University of Pavia, 27100 Pavia, Italy
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
U-Fat Chio,He-Gong Wei,Yan Zhu,et al. Design and experimental verification of a power effective Flash-SAR subranging ADC[J]. IEEE Transactions on Circuits and Systems II: Express Briefs,2010,57(8):607-611.
APA U-Fat Chio.,He-Gong Wei.,Yan Zhu.,Sai-Weng Sin.,Seng-Pan U.,...&Franco Maloberti.(2010).Design and experimental verification of a power effective Flash-SAR subranging ADC.IEEE Transactions on Circuits and Systems II: Express Briefs,57(8),607-611.
MLA U-Fat Chio,et al."Design and experimental verification of a power effective Flash-SAR subranging ADC".IEEE Transactions on Circuits and Systems II: Express Briefs 57.8(2010):607-611.
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