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A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS
Wei H.1; Chan C.-H.1; Chio U.-F.1; Sin S.-W.1; Seng-Pan U.1; Martins R.1,2; Maloberti F.3
2011-05-12
Conference Name2011 IEEE International Solid-State Circuits Conference
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages188-189
Conference Date20-24 Feb. 2011
Conference PlaceSan Francisco, CA, USA
Abstract

The successive-approximation (SA) algorithm is traditionally used for low-bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions [1]. This design uses the successive-approximation method to obtain 8b up to 400MS/s with very low power using a 1.2V supply. Key features of the architecture are a resistive DAC and a 2b-per-cycle conversion with interpolated sampling front-ends and shift registers. A cross-coupled bootstrapping network is also implemented to alleviate the signal-dependent clock feed-through. The very compact layout leads to a silicon area of 0.024 mm. © 2011 IEEE.

DOIhttp://doi.org/10.1109/ISSCC.2011.5746276
URLView the original
Language英语
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Document TypeConference paper
专题DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
Affiliation1.University of Macau, Macau, China
2.Instituto Superior Tecnico, Lisbon, Portuga
3.University of Pavia, Pavia, Italy
First Author AffilicationUniversity of Macau
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Wei H.,Chan C.-H.,Chio U.-F.,et al. A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS[C],2011:188-189.
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