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Clock-jitter sensitivity reduction in CT ΣΔ modulators using voltage-crossing detection DAC
Jiang Y.2; Cai C.-Y.2; Sin S.-W.2; U S.-P.2; Martins R.P.1,2
2011-10-13
Conference Name54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
Source PublicationMidwest Symposium on Circuits and Systems
Conference DateAUG 07-10, 2011
Conference PlaceYonsei Univ, Seoul, SOUTH KOREA
Abstract

A fixed-pulse shape current steering feedback DAC for reducing the clock-jitter sensitivity in CT ΣΔ modulators is presented. Comparing with traditional solutions for clock-jitter effect reduction, the proposed technique uses fixed-pulse shape feedback to achieve higher feedback precision. By applying voltage-crossing detection, fixed-shape feedback pulse with immunity to clock-jitter influence can be generated. A self-reset zero-crossing detector was also designed to reduce the power consumption. The proposed feedback DAC was verified in the design of a 2 order, 1-bit CT ΣΔ modulator. Full transistor level simulation results show that a 62.5dB SNDR can be achieved with a clock-jitter not larger than 5%TS. In contrast with the utilization of a general RZ feedback DAC, the proposed technique improves the SNDR by 35dB under 5%TS of clock-jitter effect. © 2011 IEEE.

DOIhttp://doi.org/10.1109/MWSCAS.2011.6026517
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Information Systems ; Engineering, Electrical & Electronic
WOS IDWOS:000296057200253
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
Recommended Citation
GB/T 7714
Jiang Y.,Cai C.-Y.,Sin S.-W.,et al. Clock-jitter sensitivity reduction in CT ΣΔ modulators using voltage-crossing detection DAC[C],2011.
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