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A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators
Wong S.-S.2; Chio U.-F.2; Chan C.-H.2; Choi H.-L.2; Sin S.-W.2; Seng-Pan U.2; Martins R.P.2
2011-12-01
Conference NameIEEE Asian Solid-State Circuits Conference 2011
Source Publication2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
Pages73-76
Conference Date14-16 Nov. 2011
Conference PlaceJeju, South Korea
Abstract

This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. The proposed topology, when compared with previous binary-search ADC architectures, further reduces the number of comparators from 2N-1 to N for N-bit precision, the comparator structure is simplified, and it can avoid both the signal dependent offsets and the kickback noise. The proposed binary-search ADC has been implemented in 65nm CMOS process and it consumes 1.63mW at an operation frequency of 500MS/s. The measurement results demonstrate that the binary-search ADC achieves 30.7dB SNDR (4.8-bit ENOB). © 2011 IEEE.

KeywordAnalog-to-digital Converter (Adc) Asynchronous Binary-search Adc Flash Adc Sar Adc
DOIhttp://doi.org/10.1109/ASSCC.2011.6123607
URLView the original
Language英语
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Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
Recommended Citation
GB/T 7714
Wong S.-S.,Chio U.-F.,Chan C.-H.,et al. A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators[C],2011:73-76.
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