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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
Chi-Hang Chan1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1,2; R.P.Martins1,3
2012-09-28
Conference Name2012 Symposium on VLSI Circuits Digest of Technical Papers
Source Publication2012 Symposium on VLSI Circuits (VLSIC)
Pages86-87
Conference Date13-15 June 2012
Conference PlaceHonolulu, HI, USA
Abstract

An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm in 65nm CMOS including on-chip offset calibration. © 2012 IEEE.

DOIhttp://doi.org/10.1109/VLSIC.2012.6243802
URLView the original
Language英语
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Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI, FST, University of Macau, Macao, China
2.Instituto Superior TécnicoAlso with Synopsys - Chipidea Microelectronics (Macau) Limited
3.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chi-Hang Chan,Yan Zhu,Sai-Weng Sin,et al. A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure[C],2012:86-87.
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