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A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
Si-Seng Wong1; U-Fat Chio1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1,2; R. P. Martins1,3
2012
Conference Name34th Annual IEEE Custom Integrated Circuits Conference (CICC)
Source PublicationProceedings of the IEEE 2012 Custom Integrated Circuits Conference
Conference Date9-12 Sept. 2012
Conference PlaceSan Jose, CA, USA
Abstract

A 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC architecture is proposed, where the ADC's front-end is built with a 5b binary-search ADC, shared by two time-interleaved 6b SAR ADCs in the 2 -stage. The design prevents the use of opamp that causes large power dissipation. Besides, a process insensitive asynchronous logic is proposed to further reduce the delay of SA loop. The ADC was fabricated in 65nm CMOS and achieves 54.6dB SNDR at 170MS/s with only 2.3mW of power consumption, leading to a FoM of 30.8fJ/conversion-step. © 2012 IEEE.

KeywordAnalog-to-digital Converter (Adc) Binary-search Adc Time-interleaved Sar Adc Two-step Adc
DOIhttp://doi.org/10.1109/CICC.2012.6330695
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000310365600114
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China
2.Also with Synopsys - Chipidea Microelectronics (Macau) Limited
3.On leave from Instituto Superior Técnico (IST)/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Si-Seng Wong,U-Fat Chio,Yan Zhu,et al. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC[C],2012.
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