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A 22.4 μw 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application
Zhijie Chen1,2; Yang Jiang2; Chenyan Cai2; He-Gong Wei2; Sai-Weng Sin2; Seng-Pan U2; Zhihua Wang2; Rui Paulo Martins2,3
2012-12-01
Conference NameIEEE Asian Solid State Circuits Conference (A-SSCC)
Source Publication2012 IEEE Asian Solid State Circuits Conference (A-SSCC)
Pages257-260
Conference DateNOV 12-14, 2012
Conference PlaceKobe, JAPAN
Abstract

A Feed-Forward (FF) multi-bit ΣΔ modulator with passive analog adder and 4-bit Successive Approximation (SA) quantizer is presented. The modulator covers the 10KHz bandwidth according to electromyography application. The design utilizes the same DAC array of the SAR quantizer to realize analog summation for the FF signal, which significantly reduces the power dissipation and the silicon area. The modulator operates at 1MS/s with 1V supply. The prototype chip implemented in 65nm CMOS achieves 80dB SNDR and 81dB DR with 22.4μW power consumption. The Figure of Merit (FoM) is 0.13 pJ/conv.-step. © 2012 IEEE.

KeywordΣδ Modulator Sar Quantizer Passive Analog Adder
DOIhttp://doi.org/10.1109/IPEC.2012.6522674
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Theory & Methods ; Engineering, Electrical & Electronic
WOS IDWOS:000392841900065
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Cited Times [WOS]:5   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Institute of Microelectronics, Tsinghua University, Beijing, China
2.State-Key Laboratory of Analog and Mixed Signal VLSI Faculty of Science and Technology, University of Macau, Macao, China
3.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Zhijie Chen,Yang Jiang,Chenyan Cai,et al. A 22.4 μw 80dB SNDR ΣΔ modulator with passive analog adder and SAR quantizer for EMG application[C],2012:257-260.
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