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Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC
Jianyu Zhong1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1,2; Rui P. Martins1,3
2012
Conference NameIEEE Asian Solid State Circuits Conference (A-SSCC)
Source Publication2012 IEEE Asian Solid State Circuits Conference (A-SSCC)
Pages153-156
Conference DateNOV 12-14, 2012
Conference PlaceKobe, JAPAN
Abstract

This paper proposes an Inter-Stage Gain Error (ISGE) calibration method devoted to correct the residue gain errors induced by the parasitic effects, non-ideal op-amp gain and capacitor mismatch, and also the mismatches for supply-derived reference voltages between two stages for Pipelined-SAR ADC. The calibration reuses the SAR ADC to estimate the overall inter-stage gain error and compensates it in the 2-stage DAC in 2 cycles, and it is implemented in a Pipelined-SAR which achieves 10b 470 MS/s in 65nm CMOS with the FoM of 31.5fJ/conv.-step by consuming only 6% of the total ADC area (0.049mm). © 2012 IEEE.

DOIhttp://doi.org/10.1109/IPEC.2012.6522648
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Theory & Methods ; Engineering, Electrical & Electronic
WOS IDWOS:000392841900039
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Citation statistics
Cited Times [WOS]:5   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Kay Lab. of Analog and Mixed Signal VLSI. Faculty of Science and Technology, University of Macau Macao, China
2.Also with Synopsys - Chipidea Microelectronics (Macau) Limited
3.On leave from Instituto Superior Técnico (IST)/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Jianyu Zhong,Yan Zhu,Sai-Weng Sin,et al. Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pipelined-SAR ADC[C],2012:153-156.
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