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A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique
Rui Wang1,2; U-Fat Chio2; Sai-Weng Sin2; Seng-Pan U2,3; Zhihua Wang1; Rui Paulo Martins2,4
2012-12-14
Conference NameEuropean Solid-State Circuits Conference
Source Publication2012 Proceedings of the ESSCIRC (ESSCIRC)
Pages265-268
Conference Date17-21 Sept. 2012
Conference PlaceBordeaux, France
Abstract

This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp. A ratio-based GEC (Gain Error Calibration) technique based on op-amp sharing is proposed to reduce the complexity of digital calibration circuit. Only one PN (Pseudo-random Number) signal is employed to perform the dither injection but calibrate multiple gain errors, and thus accelerates the convergence speed, gets rid of input signal reduction and minimizes the analog modification due to the background calibration. The effectiveness of the architecture is verified in 65-nm CMOS chips whose analog core area is 0.12 mm only. The ADC obtains an average SNDR of 63 dB and SFDR of 75.2 dB at 110MS/s consuming analog power of 11.5mW from a 1.2-V supply. Only 40 thousand points are needed to achieve desirable SNDR with the proposed calibration technique. © 2012 IEEE.

KeywordSar Adc Pipelined Digital Calibration Op-amp Sharing
DOIhttp://doi.org/10.1109/ESSCIRC.2012.6341336
URLView the original
Language英语
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Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Institute of Microelectronic, Tsinghua University, Beijing, China
2.State-Key Laboratory of Analog and Mixed Signal VLSI, FST, University of Macao, Macao, China
3.Also With Synopsys - Chipidea Microelectronics (Macau) Limited
4.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
Recommended Citation
GB/T 7714
Rui Wang,U-Fat Chio,Sai-Weng Sin,et al. A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique[C],2012:265-268.
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