A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC
Si-Seng Wong1,2; U-Fat Chio1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan U1,2; Rui Paulo Martins1,3
2013-08-05
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume48Issue:8Pages:1783-1794
Abstract

This paper presents the architecture of a 10b 170 MS/s two-step binary-search assisted time-interleaved SAR ADC. The front-end stage of this ADC is built with a 5b binary-search ADC, which is shared by two time-interleaved 6b SAR ADCs in the second-stage. The design does not use any static component such as op-amp or preamplifier that causes large dissipation of static power. DAC settling speed and power are also relaxed thanks to this architecture. Besides, the process insensitive asynchronous logic further reduces the delay of SA loop rather than using worst case delay cells to compensate the process variation problem. The ADC was fabricated in 65 nm CMOS and achieves 54.6 dB SNDR at 170 MS/s with only 2.3 mW of power consumption, leading to a FoM of 30.8 fJ/conversion-step. © 1966-2012 IEEE.

KeywordAnalog-to-digital Converter (Adc) Binary-search Adc Sar Adc Time-interleaved Two-step Adc
DOIhttp://doi.org/10.1109/JSSC.2013.2258832
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000322121900003
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Cited Times [WOS]:22   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
Corresponding AuthorSi-Seng Wong
Affiliation1.State Key Laboratory of Analog and Mixed Signal VLSI and the Faculty of Science and Technology, University of Macau, Macao, China
2.Synopsys Macau Ltd., Macao, China
3.on leave from Instituto Superior Técnico/TU, Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Si-Seng Wong,U-Fat Chio,Yan Zhu,et al. A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC[J]. IEEE Journal of Solid-State Circuits,2013,48(8):1783-1794.
APA Si-Seng Wong,U-Fat Chio,Yan Zhu,Sai-Weng Sin,Seng-Pan U,&Rui Paulo Martins.(2013).A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC.IEEE Journal of Solid-State Circuits,48(8),1783-1794.
MLA Si-Seng Wong,et al."A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC".IEEE Journal of Solid-State Circuits 48.8(2013):1783-1794.
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