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A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS
Wen-Lan Wu1; Yan Zhu1; Li Ding1; Chi-Hang Chan1; U-Fat Chio1; Sai-Weng Sin1; Seng-Pan U1,2; Rui Paulo Martins1,3
2013
Conference NameIEEE International Symposium on Circuits and Systems (ISCAS)
Source Publication2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
Pages2239-2242
Conference DateMAY 19-23, 2013
Conference PlaceBeijing, PEOPLES R CHINA
Abstract

This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced VCM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and reference noise. The proposed 8-bit SAR ADC operates at 100MS/s with 0.6V supply in 65nm CMOS. The simulation results show that the design achieves 48.8dB SNDR with only 0.524mW power. The Figure-of-Merit (FoM) is 23.35fJ/conversion-step.

DOIhttp://doi.org/10.1109/ISCAS.2013.6572322
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000332006802114
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被引频次[WOS]:6   [WOS记录]     [WOS相关记录]
Document TypeConference paper
专题INSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Kay Lab. of Analog and Mixed Signal VLSI Faculty of Science and Technology, University of Macau Macao, China
2.Also with Synopsys - Chipidea Microelectronics (Macao) Limited
3.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
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Wen-Lan Wu,Yan Zhu,Li Ding,et al. A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS[C],2013:2239-2242.
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