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A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration
Li Ding1; Wenlan Wu1; Sai-Weng Sin1; Seng-Pan U1,2; R.P.Martins1,3
2013
Conference Name9th IEEE Asian Solid-State Circuits Conference (A-SSCC)
Source Publication2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pages77-80
Conference Date11-13 Nov. 2013
Conference PlaceSingapore, Singapore
Abstract

This paper proposes acomprehensive background gain and mismatch error calibration technique for split ADC, without injecting any test signal. By employing a comparator threshold random selection method the input/output transfer characteristics of each split ADC channel is different. Based on Least Mean Square (LMS) adaptation the interstage gain error and capacitor mismatch error are corrected. All the estimations and corrections are performed in the digital domain, resulting in slight modifications of the analog circuit. The proposed calibration technique is applied on a 13-bit 60MS/s pipelined ADC. Fabricated in a 90nm CMOS process, the ADC achieves 70.8dB SNDR while consuming 63.8mW. The FoM is 377fJ/step at DC and 452 fJ/step at Nyquist. © 2013 IEEE.

DOIhttp://doi.org/10.1109/ASSCC.2013.6690986
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000330857500020
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Cited Times [WOS]:3   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China
2.Also with Synopsys - Chipidea Microelectronics (Macau) Limited
3.on leave from Instituto Superior Técnico / TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Li Ding,Wenlan Wu,Sai-Weng Sin,et al. A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration[C],2013:77-80.
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