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A 0.127-mm2, 5.6-mW, 5th-order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz clock-defined bandwidth in 65-nm CMOS
Yaohua Zhao1; Pui-In Mak1; Man-Kay Law1; Rui P. Martins1,2
2013
Conference Name9th IEEE Asian Solid-State Circuits Conference (A-SSCC)
Source Publication2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pages361-364
Conference DateNOV 11-13, 2013
Conference PlaceSingapore, SINGAPORE
Abstract

This paper proposes two techniques for improving the linearity and power efficiency of switched-capacitor (SC) circuits. The first is a high-speed switched-current-assisting (SCA) path that helps the main (folded-cascode) OTA to deliver most of the desired charge to the integration capacitor, leaving the final error correction to be completed by the main OTA. The second is a pre-charging (PC) path that assists the main OTA to speed up the charging of the load capacitor. Both SCA and PC paths share one auxiliary (differential-pair) OTA that features a high speed-to-power efficiency. The prototype is a bandwidth-scalable 5-order Butterworth SC lowpass filter (LPF) for software-defined radios. Fabricated in 65-nm CMOS, the LPF exhibits a decade-wide tunable bandwidth (1.5 to 15 MHz) solely defined by the clock, leading to a compact die size (0.127 mm). Under the same power (5.6 mW) and bandwidth (10 MHz) targets, the IIP3 reaches +23.5 dBm (+15.3 dBm) and the cutoff accuracy is 97% (82%) with (without) the SCA + PC paths. The achieved Figure-of-Merit (0.014 fJ) compares favorably with the state-of-the-art. 

KeywordBandwidth Cmos Linearity Lowpass Filter (Lpf) Operational Transconductance Amplifier (Ota) Software-defined Radio Switched Capacitor (Sc)
DOIhttp://doi.org/10.1109/ASSCC.2013.6691057
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000330857500090
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Citation statistics
Cited Times [WOS]:6   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
Affiliation1.The State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China
2.on leave from Instituto Superior Técnico /Universidade de Lisboa, Portugal.
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Yaohua Zhao,Pui-In Mak,Man-Kay Law,et al. A 0.127-mm2, 5.6-mW, 5th-order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz clock-defined bandwidth in 65-nm CMOS[C],2013:361-364.
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