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A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS
Yan Zhu1; Chi-Hang Chan1; Seng-Pan U1; R.P.Martins1,2
2013
Conference Name9th IEEE Asian Solid-State Circuits Conference (A-SSCC)
Source Publication2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pages69-72
Conference DateNOV 11-13, 2013
Conference PlaceSingapore, SINGAPORE
Abstract

This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation. © 2013 IEEE.

DOIhttp://doi.org/10.1109/ASSCC.2013.6690984
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000330857500018
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Citation statistics
Cited Times [WOS]:11   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China
2.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Yan Zhu,Chi-Hang Chan,Seng-Pan U,et al. A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS[C],2013:69-72.
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