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Micropower two-stage amplifier employing recycling current-buffer Miller compensation
Wei Wang1; Zushu Yan1; Pui-In Mak1; Man-Kay Law1; Rui P. Martins1,2
2014
Conference NameIEEE International Symposium on Circuits and Systems (ISCAS)
Source Publication2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages1889-1892
Conference DateJUN 01-05, 2014
Conference PlaceMelbourne, AUSTRALIA
Abstract

—Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1st stage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency, DC gain, dc offset and noise performances. Optimized in 0.18μm CMOS via a lowpower design procedure, the amplifier achieves >90dB DC gain, 4.5MHz unity-gain frequency and 57.2° phase margin at a 100pF capacitive load. The average slew rate and 1% settling time are 2.68V/μs and 0.239μs, respectively. The amplifier draws 22μA at a 1.2V supply.

DOIhttp://doi.org/10.1109/ISCAS.2014.6865528
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000346488600474
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Citation statistics
Cited Times [WOS]:4   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
Affiliation1.State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China
2.on leave from Instituto Superior Técnico, U of Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Wei Wang,Zushu Yan,Pui-In Mak,et al. Micropower two-stage amplifier employing recycling current-buffer Miller compensation[C],2014:1889-1892.
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