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An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC
Yan Zhu1; Chi-Hang Chan1; Seng-Pan U1,2; R.P.Martins1,3
Conference Name40th European Solid-State Circuit Conference (ESSCIRC)
Source PublicationESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)
Conference Date22-26 Sept. 2014
Conference PlaceVenezia Lido, ITALY

This paper presents a sub-ranging 6-way time-interleaved pipelined-SAR ADC that achieves 900MS/s and 9.3 ENOB in 65nm CMOS. The architecture optimization is based on a pipelined-SAR structure that obtains high-speed with an optimized number of channels, thus leading to relaxed calibration with higher efficiency in power and area consumption. The proposed channel-selection-embedded bootstrap performs sampling instants synchronization without additional components, thus effectively suppressing the spurs from time skews below -65 dBFS. The mismatch errors due to offset and gain are all solved on-chip, whose spurs are suppressed below -67 dBFS. The prototype achieves 66 dB SFDR and 51.5 dB SNDR with a Nyquist input exhibiting a FoM of 56 fJ/conv.step.

URLView the original
Indexed BySCI
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000349461900047
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Cited Times [WOS]:11   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
Faculty of Science and Technology
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI ( Faculty of Science and Technology, University of Macau, Macao, China
2.Also with Synopsys Macau Ltd.
3.On leave from Instituto Superior Técnico/Universidade de Lisboa, Portugal
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Yan Zhu,Chi-Hang Chan,Seng-Pan U,et al. An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC[C],2014:211-214.
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