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A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
Chi-Hang Chan1; Yan Zhu1; Sai-Weng Sin1; Seng-Pan (Ben) U2; Rui Paulo Martins3
2016-02-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN00189200
Volume51Issue:2Pages:365-377
Abstract

This paper presents a 4 × time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error probability at the large error magnitude, by utilizing the extended time when the comparator is at reset and the DAC at settling. The floorplan of the front-end is optimized for important interleaving clock distributions, and a master-clock-control bootstrapped-switch technique is adopted to suppress the timing-skew effect among the channels. The unit capacitor has been designed to suit for the DAC structure which allows top-plate sharing in both directions, plus, the offset is calibrated on-chip with a clocking variable biasing transistor pair at the latch. Measurement results show that the prototype can achieve 5 GS/s with a total power consumption of 5.5 mW at 1 V supply in 65 nm CMOS technology. Besides, it exhibits a 30.76 dB SNDR and 43.12 dB SFDR at Nyquist, which yields a Walden FoM of 39 fJ/conversion-step.

KeywordAnalog-to-digital Conversion Interleaving Interpolation Multibit/cycle Sar Offset Calibration
DOIhttp://doi.org/10.1109/JSSC.2015.2493167
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000370743100005
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被引频次[WOS]:8   [WOS记录]     [WOS相关记录]
Document TypeJournal article
专题INSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorChi-Hang Chan
Affiliation1.State Key Laboratory of Analog and Mixed Signal VLSI, Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao 999078, China
2.State Key Laboratory of Analog and Mixed Signal VLSI, Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao 999078, China, and also with the Synopsys Macau Ltd., Macao 999078, China
3.State Key Laboratory of Analog and Mixed Signal VLSI, Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao 999078, China, on leave from Instituto Superior Técnico, Universidade de Lisboa, Lisboa,
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
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Chi-Hang Chan,Yan Zhu,Sai-Weng Sin,et al. A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC[J]. IEEE Journal of Solid-State Circuits,2016,51(2):365-377.
APA Chi-Hang Chan,Yan Zhu,Sai-Weng Sin,Seng-Pan ,&Rui Paulo Martins.(2016).A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC.IEEE Journal of Solid-State Circuits,51(2),365-377.
MLA Chi-Hang Chan,et al."A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC".IEEE Journal of Solid-State Circuits 51.2(2016):365-377.
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