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Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques
Ming-Zhong Li1; Chio-In Ieong1; Man-Kay Law1; Pui-In Mak1; Mang-I Vai1; Sio-Hang Pun1; Rui P. Martins1,2
2016-03-07
Conference Name21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Source Publication2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Volume25-28 Jan. 2016
Pages15-16
Conference DateJAN 25-28, 2016
Conference PlaceMacau, China
Abstract

This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-μm CMOS technology, while one of them achieved the minimum energy/tap (0.0234 pJ) and 0.365 Figure-of-Merit (FoM) at 100 kHz, 0.31 V.

DOIhttp://doi.org/10.1109/ASPDAC.2016.7427979
URLView the original
Indexed BySCI
Language英语
WOS Research AreaAutomation & Control Systems ; Engineering
WOS SubjectAutomation & Control Systems ; Engineering, Electrical & Electronic
WOS IDWOS:000384642200008
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Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China
2.On leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Ming-Zhong Li,Chio-In Ieong,Man-Kay Law,et al. Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques[C],2016:15-16.
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