UM
Sub-μW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring
Chio-In Ieong2; Pui-In Mak2; Mang-I Vai2; Rui P. Martins1
2016-03-07
Conference Name21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Source Publication2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)
Volume25-28-January-2016
Pages21-22
Conference DateJAN 25-28, 2016
Conference PlaceMacau, China
Abstract

This paper describes a power-efficient processor for extracting the timing of QRS complex from digitized ECG, based on the hardware-efficient architecture of quadratic spline wavelet transform (QSWT) and maxima modulus pair recognition (MMPR). The processor succeeds in saving the wireless system's power by 6×.

DOIhttp://doi.org/10.1109/ASPDAC.2016.7427982
URLView the original
Indexed BySCI
Language英语
WOS Research AreaAutomation & Control Systems ; Engineering
WOS SubjectAutomation & Control Systems ; Engineering, Electrical & Electronic
WOS IDWOS:000384642200011
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Cited Times [WOS]:1   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionUniversity of Macau
Affiliation1.State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China
2.On leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal
Recommended Citation
GB/T 7714
Chio-In Ieong,Pui-In Mak,Mang-I Vai,et al. Sub-μW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring[C],2016:21-22.
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