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An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
Yan Zhu1; Chi-Hang Chan1; Seng-Pan U2; Rui Paulo Martins2,3
2016-05-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN00189200
Volume51Issue:5Pages:1223-1234
Abstract

This paper presents an 11 bit 450 MS/s three-way time-interleaved (TI) subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC). The proposed hybrid architecture combines the design benefits of different ADC structures to achieve a high conversion rate and accuracy with good power efficiency. The design employs multiple offset calibration schemes to compensate the offset mismatches at each stage. The solutions require less calibration efforts, thus allowing the ADC to achieve a compact area. Furthermore, a dynamic SAR controller embedded with error-decision-correction (EDC) logic is proposed to reduce large transition error. Measurement results on a 65 nm CMOS prototype operated at 450 MS/s and 1.2 V supply show 7.4 mW total power consumption with a peak signal-to-noise distortion ratio (SNDR) of 60.8 dB and an FOM of 32 fJ/conv.step at Nyquist.

KeywordOffset Calibration Pipelined-successive Approximation Register (Sar) Analog-to-digital Converter (Adc) Sar Logic
DOIhttp://doi.org/10.1109/JSSC.2016.2522762
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000376885800014
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Cited Times [WOS]:16   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorYan Zhu
Affiliation1.State Key Laboratory of Analog and Mixed Signal, University of Macau, Macao, China
2.Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macao, China, and also with Synopsys Macau Ltd., Macao, China
3.Instituto Superior Técnico/Universidade de Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Yan Zhu,Chi-Hang Chan,Seng-Pan U,et al. An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS[J]. IEEE Journal of Solid-State Circuits,2016,51(5):1223-1234.
APA Yan Zhu,Chi-Hang Chan,Seng-Pan U,&Rui Paulo Martins.(2016).An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS.IEEE Journal of Solid-State Circuits,51(5),1223-1234.
MLA Yan Zhu,et al."An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS".IEEE Journal of Solid-State Circuits 51.5(2016):1223-1234.
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