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A high resolution multi-bit incremental converter insensitive to DAC mismatch error
Biao Wang1; Sai-Weng Sin1; Seng-Pan U1,2; R. P. Martins1,3
2016-07-22
Conference Name12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Source Publication2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Conference DateJUN 27-30, 2016
Conference PlaceLisbon, Portugal
Abstract

This paper presents a second order multi-bit incremental analog-to-digital converter with two-phase feedback DAC control logic, insensitive to capacitor mismatches and with enhanced performance in multi-bit implementation. Besides, the proposed technique eliminates the complexity of dynamic element matching and relaxes the Op-amp’s settling time. Behavioral simulations show that it can achieve ૚૚૞. ૞૞ dB SNDR at ૚૛ૡ clock cycles using a ૠ -bit quantizer without dynamic element matching.

KeywordHigh Resolution Incremental Converter Multi-bit Quantizer Insensitive To Dac Mismatch
DOIhttp://doi.org/10.1109/PRIME.2016.7519459
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000390689500011
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.State-Key Laboratory of Analog and Mixed Signal VLSI, Dept. of ECE, FST, University of Macau, Macao, China
2.Also with Synopsys Macau Ltd
3.On leave from Instituto Superior Técnico / Universidade de Lisboa, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Biao Wang,Sai-Weng Sin,Seng-Pan U,et al. A high resolution multi-bit incremental converter insensitive to DAC mismatch error[C],2016.
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