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A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM
Chee-Cheow Lim1; Harikrishnan Ramiah1; Jun Yin2; Pui-In Mak2; Rui P. Martins2,3
2016-07-29
Conference NameIEEE International Symposium on Circuits and Systems (ISCAS)
Source Publication2016 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages2759-2762
Conference Date22-25 May 2016
Conference PlaceMontreal, QC, Canada
Abstract

This paper proposes a dual-layer patterned floating shield (DL-PFS) technique for Silicon-based on-chip spiral inductors. By optimally utilizing the two lowest metal layer strips to shield the inductor from the substrate, electromagnetic (EM) simulations show 40% improvement of the Q factor when compared with the conventional approach. Designed and simulated in 0.13-μm CMOS, the DL-PFS inductor in a class-B VCO achieves 6.6-dB lower phase noise, and 34% power savings. The VCO also exhibits 9.7-to-10.93 GHz tunability, and -123-dBc/Hz phase noise at a 3 MHz offset. The power consumption is 1.64 mW at 0.6 V, leading to a state-of-the-art FoM of 190.5 dBc/Hz.

KeywordInductor Rfic Vco Dual-layer Patterned Floating Shield
DOIhttp://doi.org/10.1109/ISCAS.2016.7539164
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000390094702228
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被引频次[WOS]:1   [WOS记录]     [WOS相关记录]
Document TypeConference paper
专题INSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia
2.State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China
3.on leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal
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Chee-Cheow Lim,Harikrishnan Ramiah,Jun Yin,et al. A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM[C],2016:2759-2762.
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