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A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS
Jianwei Liu1,2; Chi-Hang Chan1; Sai-Weng Sin1,2; Seng-Pan U1,2; Rui Paulo Martins1,2
2016-08-01
Source PublicationJournal of Semiconductor Technology and Science
ISSN15981657
Volume16Issue:4Pages:395-404
Abstract

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional 2-1 to 2 in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the 2 comparators needs to be calibrated. The offset in SR-latches is within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

Keyword4x Time-domain Interpolation Flash Adc Sr-latch Time Comparator
DOI10.5573/JSTS.2016.16.4.395
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering ; Physics
WOS SubjectEngineering, Electrical & Electronic ; Physics, Applied
WOS IDWOS:000393187800003
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Citation statistics
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
Corresponding AuthorRui Paulo Martins
Affiliation1.State Key Laboratory of Analog and Mixed-Signal VLSI
2.Dept. of ECE, University of Macau, Macao, China
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Jianwei Liu,Chi-Hang Chan,Sai-Weng Sin,et al. A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS[J]. Journal of Semiconductor Technology and Science,2016,16(4):395-404.
APA Jianwei Liu,Chi-Hang Chan,Sai-Weng Sin,Seng-Pan U,&Rui Paulo Martins.(2016).A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS.Journal of Semiconductor Technology and Science,16(4),395-404.
MLA Jianwei Liu,et al."A 4x time-domain interpolation 6-bit 3.4 Gs/s 12.6 mw flash ADC in 65 nm CMOS".Journal of Semiconductor Technology and Science 16.4(2016):395-404.
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