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A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output
Yin J.2; Mak P.-I.2; Maloberti F.1; Martins R.P.2
2016-12-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN00189200
Volume51Issue:12Pages:2979-2991
Abstract

This paper describes a time-interleaved (TI) ring-VCO (RVCO) exhibiting an improved phase noise over a wide range of frequency offsets, an extended tuning range and an inherent divided output. Such features are achieved by substantially increasing the number of delay stages in a RVCO, such that the rich multi-phase sub-outputs can be combined through a time-interleaved method, generating a high-frequency output with a significantly lowered 1/f phase noise corner (f). The critical block is the phase combiner, which features a timing window to minimize the delay offset and mismatch. A reconfigurable TI factor extends the tuning range over the same range of supply voltage (VDD). The prototype is a 35-stage dual-mode TI-RVCO occupying 0.003 mm in 65 nm CMOS, and has a selectable TI factor of 5 and 7. The measured f is 150 kHz at 3.47 GHz, which is 6.2× less than that of a typical 5-stage RVCO. The tuning range covers 1.7 to 3.5 GHz (68.5%) over V = 0.7 to 1 V. The multi-phase sub-outputs are the inherent divided output (÷ 5 or ÷ 7) that can be directly utilized in a PLL to save area and power.

Keyword1/f3 Phase Noise Corner Divided Output Flicker Noise Impulse Sensitivity Function (Isf) Phase Combiner Phase Noise Ring Voltage-controlled Oscillator (Rvco) Supply Voltage Time-interleaved (Ti).
DOI10.1109/JSSC.2016.2597847
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000390420300016
Fulltext Access
Citation statistics
Cited Times [WOS]:8   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorYin J.; Mak P.-I.; Maloberti F.; Martins R.P.
Affiliation1.Università degli Studi di Pavia
2.Universidade de Macau
Recommended Citation
GB/T 7714
Yin J.,Mak P.-I.,Maloberti F.,et al. A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output[J]. IEEE Journal of Solid-State Circuits,2016,51(12):2979-2991.
APA Yin J.,Mak P.-I.,Maloberti F.,&Martins R.P..(2016).A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output.IEEE Journal of Solid-State Circuits,51(12),2979-2991.
MLA Yin J.,et al."A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output".IEEE Journal of Solid-State Circuits 51.12(2016):2979-2991.
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