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Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching
Dezhi Xing1,2; Yan Zhu1; Chi-Hang Chan1; Sai-Weng Sin1,2; Fan Ye1,3; Junyan Ren1,3; Seng-Pan U1,2,4; Rui Paulo Martins1,2,5
2017-03-01
Source PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN10638210
Volume25Issue:3Pages:1168-1172
Abstract

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial V-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm. The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.

KeywordCommon Mode Variation Partial Vcm-based Switching Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)
DOI10.1109/TVLSI.2016.2610864
URLView the original
Indexed BySCI
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000395894000034
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Cited Times [WOS]:5   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorDezhi Xing
Affiliation1.Univ Macau, State Key Lab Analog & Mixed Signal, Macau 999078, Peoples R China
2.Univ Macau, Fac Sci & Technol, Dept Elect & Comp Engn, Macau 999078, Peoples R China
3.Fudan Univ, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China
4.Synopsys Macau Ltd, Macau 999078, Peoples R China
5.Univ Lisbon, Inst Super Tecn, P-1649004 Lisbon, Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Dezhi Xing,Yan Zhu,Chi-Hang Chan,et al. Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2017,25(3):1168-1172.
APA Dezhi Xing.,Yan Zhu.,Chi-Hang Chan.,Sai-Weng Sin.,Fan Ye.,...&Rui Paulo Martins.(2017).Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,25(3),1168-1172.
MLA Dezhi Xing,et al."Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial Vcm-Based Switching".IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25.3(2017):1168-1172.
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