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A 5-bit 2 GS/s binary-search ADC with charge-steering comparators
Chio, U-Fat1,2; Sin S.-W.1,2; Seng-Pan U.2,3; Maloberti F.4; Martins R.P.2,4
2017-12-26
Conference NameIEEE Asian Solid-State Circuits Conference (A-SSCC)
Source Publication2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Pages221-224
Conference DateNOV 06-08, 2017
Conference PlaceSeoul, SOUTH KOREA
CountrySOUTH KOREA
Abstract

This paper presents a 5-bit 2GS/s binary-search ADC. The proposed architecture prevents the use of a decoder to avoid the path delay racing between control signals and clock phases; thence the bit latency reduces to 1 single comparator delay only. We also propose a dynamic charge-steering comparator to quantize each bit quickly. Besides, we present well-balanced 1-of-N-to-Binary encoders to transform the output code with low power. This ADC consumes 3.9mW at 2GS/s in 65nm CMOS. It achieves a SNDR of 28 dB at Nyquist rate resulting in a FoM of 95 fJ/conv.-step.

KeywordBinary-search Adc Asynchronous Charge-steering
DOIhttp://doi.org/10.1109/ASSCC.2017.8240256
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000426511300056
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Citation statistics
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Univ Macau, State Key Lab Analog & Mixed Signal VLSI, Fac Sci & Technol, Macau, Peoples R China
2.Univ Macau, Dept ECE, Fac Sci & Technol, Macau, Peoples R China
3.Synopsys Macau Ltd, Macau, Peoples R China
4.Univ Pavia, Dept Elect Comp & Biomed Engn, Pavia, Italy
5.Univ Lisbon, Inst Super Tecn, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Chio, U-Fat,Sin S.-W.,Seng-Pan U.,et al. A 5-bit 2 GS/s binary-search ADC with charge-steering comparators[C],2017:221-224.
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