UM
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM
Shiheng Yang1; Jun Yin1; Pui-In Mak1; Rui P. Martins1,2
2018-03-08
Conference Name65th IEEE International Solid-State Circuits Conference (ISSCC)
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume61
Pages118-120
Conference DateFEB 11-15, 2018
Conference PlaceSan Francisco, CA
Abstract

Multiplying delay-locked loops (MDLL) and injection-locked clock multipliers (ILCM) have shown improved jitter performance in recent years [1-5], but their PLL-based frequency-tracking loops (FTLs) for securing performance against frequency and PVT variations are area and power hungry. In [1], the frequency (F) is tracked by a replica-delay cell of the VCO, such that the intrinsic phase information is preserved under reference injection (REF-INJ). Regrettably an analog FTL is susceptible to noise and mismatch from the charge pump, demanding more area (loop filter: 0.01mm) and power (charge pump: 0.8mW) to limit the in-band jitter deterioration.

DOIhttp://doi.org/10.1109/ISSCC.2018.8310212
URLView the original
Indexed BySCI
Language英语
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000459205600042
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Citation statistics
Cited Times [WOS]:10   [WOS Record]     [Related Records in WOS]
Document TypeConference paper
CollectionUniversity of Macau
Affiliation1.University of Macau, Macau, China
2.Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Shiheng Yang,Jun Yin,Pui-In Mak,et al. A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM[C],2018:118-120.
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